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ucc27211a slusbl4c ? august 2013 ? revised october 2015 ucc27211a 120-v boot, 4-a peak, high-frequency high-side and low-side driver 1 features 2 applications 1 ? drives two n-channel mosfets in high-side ? power supplies for telecom, datacom, and and low-side configuration with independent merchant inputs ? half-bridge and full-bridge converters ? maximum boot voltage 120-v dc ? push-pull converters ? 4-a sink, 4-a source output currents ? high voltage synchronous-buck converters ? 0.9- pullup and pulldown resistance ? two-switch forward converters ? input pins can tolerate ? 10 v to +20 v and are ? active-clamp forward converters independent of supply voltage range ? class-d audio amplifiers ? ttl or pseudo-cmos compatible input versions 3 description ? 8-v to 17-v vdd operating range, (20-v abs max) the ucc27211a driver is based on the popular ucc27201 mosfet drivers; but, this device offers ? 7.2-ns rise and 5.5-ns fall time with 1000-pf several significant performance improvements. peak load output pullup and pulldown current has been ? fast propagation delay times (20-ns typical) increased to 4-a source and 4-a sink, and pullup and ? 4-ns delay matching pulldown resistance have been reduced to 0.9 , and thereby allows for driving large power mosfets with ? symmetrical undervoltage lockout for high-side minimized switching losses during the transition and low-side driver through the miller plateau of the mosfet. the input ? all industry standard packages available structure can directly handle ? 10 vdc, which ? soic-8 increases robustness and also allows direct interface to gate-drive transformers without using rectification ? 4-mm 4-mm son-8 diodes. the inputs are also independent of supply ? 4-mm 4-mm son-10 voltage and have a 20-v maximum rating. ? specified from ? 40 to +140 c device information (1) part number package body size (nom) soic (8) 4.90 mm 3.91 mm ucc27211a vson (8) 4.00 mm 4.00 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. typical application diagram propagation delays vs supply voltage 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. referencedesign 0 4 8 12 16 20 24 28 32 8 12 16 20 v dd =v hb ? supply voltage (v) propagation delay (ns) tdlrrtdlff tdhrr tdhff t=25c pwm controller +12v isolation and feedback +100v secondary side circuit hi control drive lo drive hi v dd ucc27211a vss li hbho hs lo udg-13114 productfolder sample &buy technical documents tools & software support &community
ucc27211a slusbl4c ? august 2013 ? revised october 2015 www.ti.com table of contents 8.1 overview ................................................................. 12 1 features .................................................................. 1 8.2 functional block diagram ....................................... 13 2 applications ........................................................... 1 8.3 feature description ................................................. 13 3 description ............................................................. 1 8.4 device functional modes ........................................ 14 4 revision history ..................................................... 2 9 application and implementation ........................ 15 5 description (continued) ......................................... 3 9.1 application information ............................................ 15 6 pin configuration and functions ......................... 4 9.2 typical application .................................................. 15 7 specifications ......................................................... 5 10 power supply recommendations ..................... 20 7.1 absolute maximum ratings ...................................... 5 11 layout ................................................................... 20 7.2 esd ratings .............................................................. 5 11.1 layout guidelines ................................................. 20 7.3 recommended operating conditions ....................... 5 11.2 layout example .................................................... 21 7.4 thermal information .................................................. 6 11.3 thermal considerations ........................................ 21 7.5 electrical characteristics ........................................... 6 12 device and documentation support ................. 22 7.6 switching characteristics: propagation delays ........ 7 12.1 documentation support ........................................ 22 7.7 switching characteristics: delay matching ............... 7 12.2 community resources .......................................... 22 7.8 switching characteristics: output rise and fall 12.3 trademarks ........................................................... 22 time ........................................................................... 7 12.4 electrostatic discharge caution ............................ 22 7.9 switching characteristics: miscellaneous ................. 7 12.5 glossary ................................................................ 22 7.10 typical characteristics ............................................ 9 13 mechanical, packaging, and orderable 8 detailed description ............................................ 12 information ........................................................... 22 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision b (september 2013) to revision c page ? added esd ratings table, feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section ................................................................................................. 1 ? changed powerpad to thermal pad throughout document .................................................................................................. 1 ? removed the ucc27210a device from the data sheet ......................................................................................................... 1 changes from revision a (august 2013) to revision b page ? changed marketing status from product preview to production data. .................................................................................... 1 changes from original (august 2013) to revision a page ? added note 2 to the terminal functions table. ..................................................................................................................... 4 ? changed repetitive pulse data from ? 18 v to ? (24 v ? vdd). .............................................................................................. 5 ? added additional details to note 2. ......................................................................................................................................... 5 ? changed voltage on hs, v hs (repetitive pulse < 100 ns) data from ? 15 to ? (24 v ? vdd). ................................................. 5 2 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: ucc27211a
ucc27211a www.ti.com slusbl4c ? august 2013 ? revised october 2015 5 description (continued) the switching node of the ucc27211a (hs pin) can handle ? 18-v maximum, which allows the high-side channel to be protected from inherent negative voltages caused by parasitic inductance and stray capacitance. the ucc27210a (pseudo-cmos inputs) and ucc27211a (ttl inputs) have increased hysteresis that allows for interface to analog or digital pwm controllers with enhanced noise immunity. the low-side and high-side gate drivers are independently controlled and matched to 2 ns between the turnon and turnoff of each other. an on-chip 120-v rated bootstrap diode eliminates the external discrete diodes. undervoltage lockout is provided for both the high-side and the low-side drivers which provides symmetric turnon and turnoff behavior and forces the outputs low if the drive voltage is below the specified threshold. the ucc27211a device is offered in 8-pin soic (d) and 8-pin vson (drm) packages. copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 3 product folder links: ucc27211a
ucc27211a slusbl4c ? august 2013 ? revised october 2015 www.ti.com 6 pin configuration and functions d package drm package 8-pin soic 8-pin vson top view top view pin functions pin i/o description name no. high-side bootstrap supply. the bootstrap diode is on-chip but the external bootstrap capacitor is required. connect positive side of the bootstrap capacitor to this pin. typical range of hb bypass hb 2 p capacitor is 0.022 f to 0.1 f. the capacitor value is dependant on the gate charge of the high- side mosfet and must also be selected based on speed and ripple criteria. hi 5 i high-side input. (1) ho 3 o high-side output. connect to the gate of the high-side power mosfet. high-side source connection. connect to source of high-side power mosfet. connect the hs 4 p negative side of bootstrap capacitor to this pin. li 6 i low-side input. (1) lo 8 o low-side output. connect to the gate of the low-side power mosfet. positive supply to the lower-gate driver. de-couple this pin to v ss (gnd). typical decoupling vdd 1 p capacitor range is 0.22 f to 4.7 f (see (2) ). vss 7 ? negative supply terminal for the device that is generally grounded. utilized on the drm package only. electrically referenced to v ss (gnd). connect to a large thermal pad (3) ? thermal mass trace or gnd plane to dramatically improve thermal performance. (1) hi or li input is assumed to connect to a low impedance source signal. the source output impedance is assumed less than 100 . if the source impedance is greater than 100 , add a bypassing capacitor, each, between hi and vss and between li and vss. the added capacitor value depends on the noise levels presented on the pins, typically from 1 nf to 10 nf should be effective to eliminate the possible noise effect. when noise is present on two pins, hi or li, the effect is to cause ho and lo malfunctions to have wrong logic outputs. (2) for cold temperature applications ti recommends the upper capacitance range. follow the layout guidelines for pcb layout. (3) the thermal pad is not directly connected to any leads of the package; however, it is electrically and thermally connected to the substrate which is the ground of the device. 4 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: ucc27211a 1 2 3 4 8 7 6 5 vdd hb ho hs lovss li hi 1 2 3 4 8 7 6 5 vdd hb hohs vss exposed thermal die pad * lo lihi
ucc27211a www.ti.com slusbl4c ? august 2013 ? revised october 2015 7 specifications 7.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit supply voltage range, v dd (2) , v hb ? v hs ? 0.3 20 v input voltages on li and hi, v li , v hi ? 10 20 v dc ? 0.3 v dd + 0.3 output voltage on lo, v lo v repetitive pulse < 100 ns (3) ? 2 v dd + 0.3 dc v hs ? 0.3 v hb + 0.3 output voltage on ho, v ho v repetitive pulse < 100 ns (3) v hs ? 2 v hb + 0.3 dc ? 1 115 voltage on hs, v hs v repetitive pulse < 100 ns (3) ? (24 v ? vdd) 115 voltage on hb, v hb ? 0.3 120 v operating virtual junction temperature range, t j ? 40 150 c storage temperature, t stg ? 65 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltages are with respect to vss unless otherwise noted. currents are positive into and negative out of the specified terminal. (3) verified at bench characterization. vdd is the value used in an application design. 7.2 esd ratings value unit human-body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v (esd) electrostatic discharge v charged-device model (cdm), per jedec specification jesd22- 1000 c101 (2) (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 7.3 recommended operating conditions all voltages are with respect to v ss ; currents are positive into and negative out of the specified terminal. ? 40 c < t j = t a < 140 c (unless otherwise noted) min nom max unit supply voltage range, v dd , v hb ? v hs 8 12 17 v voltage on hs, v hs ? 1 105 v voltage on hs, v hs (repetitive pulse < 100 ns) ? (24 v ? vdd) 110 v v hs + 8, v hs + 17, voltage on hb, v hb v v dd ? 1 115 voltage slew rate on hs 50 v/ns operating junction temperature ? 40 140 c copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 5 product folder links: ucc27211a
ucc27211a slusbl4c ? august 2013 ? revised october 2015 www.ti.com 7.4 thermal information ucc27211a thermal metric (1) d (soic) drm (son) unit 8 pins 8 pins r ja junction-to-ambient thermal resistance 111.8 37.7 c/w r jc(top) junction-to-case (top) thermal resistance 56.9 47.2 c/w r jb junction-to-board thermal resistance 53.0 9.6 c/w jt junction-to-top characterization parameter 7.8 2.8 c/w jb junction-to-board characterization parameter 52.3 9.4 c/w r jc(bot) junction-to-case (bottom) thermal resistance n/a 3.6 c/w (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953 . 7.5 electrical characteristics v dd = v hb = 12 v, v hs = v ss = 0 v, no load on lo or ho, t a = t j = ? 40 c to 140 c, (unless otherwise noted) parameter test condition min typ max unit supply currents i dd v dd quiescent current v(li) = v(hi) = 0 v 0.05 0.085 0.17 ma 2.1 2.6 6.5 ma i ddo v dd operating current f = 500 khz, c load = 0 2.1 2.5 6.5 ma i hb boot voltage quiescent current v(li) = v(hi) = 0 v 0.015 0.065 0.1 ma i hbo boot voltage operating current f = 500 khz, c load = 0 1.5 2.5 5.1 ma i hbs hb to v ss quiescent current v(hs) = v(hb) = 115 v 0.0005 1 a i hbso hb to v ss operating current f = 500 khz, c load = 0 0.07 1.2 ma input v hit input voltage threshold 1.9 2.3 2.7 v v lit input voltage threshold 1.3 1.6 1.9 v v ihys input voltage hysteresis 700 mv r in input pulldown resistance 68 k under-voltage lockout (uvlo) v ddr v dd turnon threshold 6.2 7 7.8 v v ddhys hysteresis 0.5 v v hbr v hb turnon threshold 5.6 6.7 7.9 v v hbhys hysteresis 1.1 v bootstrap diode v f low-current forward voltage i vdd-hb = 100 a 0.65 0.8 v v fi high-current forward voltage i vdd-hb = 100 ma 0.85 0.95 v r d dynamic resistance, vf/ i i vdd-hb = 100 ma and 80 ma 0.3 0.5 0.85 lo gate driver v lol low-level output voltage i lo = 100 ma 0.05 0.1 0.19 v v loh high level output voltage i lo = ? 100 ma, v loh = v dd ? v lo 0.1 0.16 0.29 v peak pull-up current (1) v lo = 0 v 3.7 a peak pull-down current (1) v lo = 12 v 4.5 a ho gate driver v hol low-level output voltage i ho = 100 ma 0.05 0.1 0.19 v v hoh high-level output voltage i ho = ? 100 ma, v hoh = v hb ? v ho 0.1 0.16 0.29 v peak pull-up current (1) v ho = 0 v 3.7 a peak pull-down current (1) v ho = 12 v 4.5 a (1) ensured by design. 6 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: ucc27211a
ucc27211a www.ti.com slusbl4c ? august 2013 ? revised october 2015 7.6 switching characteristics: propagation delays over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit t dlff v li falling to v lo falling 10 16 30 ns t dhff v hi falling to v ho falling 10 16 30 ns c load = 0 t dlrr v li rising to v lo rising 10 20 42 ns t dhrr v hi rising to v ho rising 10 20 42 ns 7.7 switching characteristics: delay matching over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit t j = 25 c 4 9.5 t mon from ho off to lo on ns t j = ? 40 c to 140 c 4 17 t j = 25 c 4 9.5 t moff from lo off to ho on ns t j = ? 40 c to 140 c 4 17 7.8 switching characteristics: output rise and fall time over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit t r lo rise time 7.2 ns c load = 1000 pf, from 10% to 90% t r ho rise time 7.2 ns t f lo fall time 5.5 ns c load = 1000 pf, from 90% to 10% t f ho fall time 5.5 ns t r lo, ho c load = 0.1 f, (3 v to 9 v) 0.36 0.6 s t f lo, ho c load = 0.1 f, (9 v to 3 v) 0.15 0.4 s 7.9 switching characteristics: miscellaneous over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit minimum input pulse width that changes the 50 ns output bootstrap diode turnoff time (1) (2) i f = 20 ma, i rev = 0.5 a (3) 20 ns (1) ensured by design. (2) i f : forward current applied to bootstrap diode, i rev : reverse current applied to bootstrap diode. (3) typical values for t a = 25 c. copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 7 product folder links: ucc27211a
ucc27211a slusbl4c ? august 2013 ? revised october 2015 www.ti.com figure 1. timing diagram 8 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: ucc27211a input (hi, li) output (ho, lo) t mon t moff li hi lo ho t dlrr , t dhrr t dlff , t dhff
ucc27211a www.ti.com slusbl4c ? august 2013 ? revised october 2015 7.10 typical characteristics figure 2. quiescent current vs supply voltage figure 3. idd operating current vs frequency figure 4. idd operating current vs frequency figure 5. boot voltage operating current vs frequency (hb to hs) figure 6. input threshold vs supply voltage figure 7. input thresholds vs temperature copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 9 product folder links: ucc27211a ?1 0 1 2 3 4 5 6 8 12 16 20 v dd ? supply voltage (v) hi, li ? input threshold voltage (v) risingfalling t = 25c ?1 0 1 2 3 4 5 6 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) hi, li ? input threshold voltage (v) risingfalling v dd = 12v 0.01 0.1 1 10 100 10 100 1000 frequency (khz) i ddo ? operating current (ma) c l =0pf, t=?40c c l =0pf, t=25c c l =0pf, t=140c c l =1000pf, t=25c c l =1000pf, t=140c c l =4700pf, t=140c v dd = 12v 0.01 0.1 1 10 100 10 100 1000 frequency (khz) i hbo ? operating current (ma) c l =0pf, t=?40c c l =0pf, t=25c c l =0pf, t=140c c l =1000pf, t=25c c l =1000pf, t=140c c l =4700pf, t=140c v hb ? v hs = 12v 0.01 0.1 1 10 100 10 100 1000 frequency (khz) i ddo ? operating current (ma) c l =0pf, t=?40c c l =0pf, t=25c c l =0pf, t=140c c l =1000pf, t=25c c l =1000pf, t=140c c l =4700pf, t=140c v dd = 12v g002 0 20 40 60 80 100 0 2 4 6 8 10 12 14 16 18 20 v dd = v hb ? supply voltage (v) i dd , i hb ? quiescent current (a) i dd i hb t = 25c
ucc27211a slusbl4c ? august 2013 ? revised october 2015 www.ti.com typical characteristics (continued) figure 8. lo and ho high-level output voltage figure 9. lo and ho low-level output voltage vs temperature vs temperature figure 10. undervoltage lockout threshold figure 11. undervoltage lockout threshold hysteresis vs temperature vs temperature figure 12. propagation delays vs temperature figure 13. propagation delays vs temperature 10 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: ucc27211a 0 4 8 12 16 20 24 28 32 36 40 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) propagation delay (ns) tdlrrtdlff tdhrr tdhff v dd =v hb =12v 0 8 16 24 32 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) propagation delay (ns) tdlrrtdlff tdhrr tdhff v dd =v hb =12v 5.2 5.6 6 6.4 6.8 7.2 7.6 8 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) threshold (v) vdd rising thresholdhb rising threshold g009 0 0.3 0.6 0.9 1.2 1.5 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) hysteresis (v) vdd uvlo hysteresishb uvlo hysteresis g010 0 0.04 0.08 0.12 0.16 0.2 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) v ol ? lo/ho output voltage (v) v dd =v hb =8v v dd =v hb =12v v dd =v hb =16v v dd =v hb =20v i ho =i lo = 100ma 0 0.04 0.08 0.12 0.16 0.2 0.24 0.28 0.32 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) v oh ? lo/ho output voltage (v) v dd =v hb =8v v dd =v hb =12v v dd =v hb =16v v dd =v hb =20v i ho =i lo = 100ma
ucc27211a www.ti.com slusbl4c ? august 2013 ? revised october 2015 typical characteristics (continued) figure 15. delay matching vs temperature figure 14. propagation delays vs supply voltage figure 16. output current vs output voltage figure 17. diode current vs diode voltage copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 11 product folder links: ucc27211a 0 4 8 12 16 20 24 28 32 8 12 16 20 v dd =v hb ? supply voltage (v) propagation delay (ns) tdlrrtdlff tdhrr tdhff t=25c 0 1 2 3 4 5 0 2 4 6 8 10 12 v lo , v ho ? output voltage (v) i lo , i ho ? output current (a) pull down currentpull up current v dd =v hb =12v g016 0.001 0.01 0.1 1 10 100 500 550 600 650 700 750 800 850 diode voltage (mv) diode current (ma) g017 ?2 0 2 4 6 8 10 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) delay matching (ns) tmon tmoff v dd =v hb =12v
ucc27211a slusbl4c ? august 2013 ? revised october 2015 www.ti.com 8 detailed description 8.1 overview the ucc27211a devices represent texas instruments ? latest generation of high-voltage gate drivers, which are designed to drive both the high-side and low-side of n-channel mosfets in a half- and full-bridge or synchronous-buck configuration. the floating high-side driver can operate with supply voltages of up to 120 v, which allows for n-channel mosfet control in half-bridge, full-bridge, push-pull, two-switch forward, and active clamp forward converters. the ucc27211a devices feature 4-a source and sink capability, industry best-in-class switching characteristics and a host of other features listed in table 1 . these features combine to ensure efficient, robust and reliable operation in high-frequency switching power circuits. table 1. ucc27211a highlights feature benefit high peak current ideal for driving large power mosfets with 4-a source and sink current with 0.9- output resistance minimal power loss (fast-drive capability at miller plateau) increased robustness and ability to handle undershoot and input pins (hi and li) can directly handle ? 10 vdc up to 20 vdc overshoot can interface directly to gate-drive transformers without having to use rectification diodes. 120-v internal boot diode provides voltage margin to meet telecom 100-v surge requirements allows the high-side channel to have extra protection from inherent switch node (hs pin) able to handle ? 18 v maximum for 100 ns negative voltages caused by parasitic inductance and stray capacitance robust esd circuitry to handle voltage spikes excellent immunity to large dv/dt conditions best-in-class switching characteristics and extremely low-pulse 18-ns propagation delay with 7.2-ns rise time and 5.5-ns fall time transmission distortion 2-ns (typ) delay matching between channels avoids transformer volt-second offset in bridge symmetrical uvlo circuit ensures high-side and low-side shut down at the same time cmos optimized threshold or ttl optimized thresholds with complementary to analog or digital pwm controllers; increased increased hysteresis hysteresis offers added noise immunity in ucc27211a, the high side and low side each have independent inputs that allow maximum flexibility of input control signals in the application. the boot diode for the high-side driver bias supply is internal to the ucc27211a. the ucc27210a is the pseudo-cmos compatible input version and the ucc27211a is the ttl or logic compatible version. the high-side driver is referenced to the switch node (hs), which is typically the source pin of the high-side mosfet and drain pin of the low-side mosfet. the low-side driver is referenced to v ss , which is typically ground. ucc27211a functions are divided into the input stages, uvlo protection, level shift, boot diode, and output driver stages. 12 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: ucc27211a
ucc27211a www.ti.com slusbl4c ? august 2013 ? revised october 2015 8.2 functional block diagram 8.3 feature description 8.3.1 input stages the input stages provide the interface to the pwm output signals. the input impedance is 100-k nominal and input capacitance is approximately 2 pf. the 100 k is a pulldown resistance to v ss (ground). the pseudo- cmos input structure has been designed to provide large hysteresis and at the same time to allows interfacing to a multitude of analog or digital pwm controllers. in some cmos designs, the input thresholds are determined as a percentage of vdd. by doing so, the high-level input threshold can become unreasonably high and unusable. the device recognizes the fact that vdd levels are trending downward and it therefore provides a rising threshold with 5.0 v (typical) and falling threshold with 3.2 v (typical). the input hysteresis of the is 1.8 v (typical). the input stages of the ucc27211a have impedance of 70-k nominal and input capacitance is approximately 2 pf. pulldown resistance to v ss (ground) is 70 k . the logic level compatible input provides a rising threshold of 2.3 v and a falling threshold of 1.6 v. 8.3.2 undervoltage lockout (uvlo) the bias supplies for the high-side and low-side drivers have uvlo protection. v dd as well as v hb to v hs differential voltages are monitored. the v dd uvlo disables both drivers when v dd is below the specified threshold. the rising v dd threshold is 7.0 v with 0.5-v hysteresis. the vhb uvlo disables only the high-side driver when the v hb to v hs differential voltage is below the specified threshold. the v hb uvlo rising threshold is 6.7 v with 1.1-v hysteresis. 8.3.3 level shift the level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to the switch node (hs). the level shift allows control of the ho output referenced to the hs pin and provides excellent delay matching with the low-side driver. 8.3.4 boot diode the boot diode necessary to generate the high-side bias is included in the ucc27211a family of drivers. the diode anode is connected to v dd and cathode connected to v hb . with the v hb capacitor connected to hb and the hs pins, the v hb capacitor charge is refreshed every switching cycle when hs transitions to ground. the boot diode provides fast recovery times, low diode resistance, and voltage rating margin to allow for efficient and reliable operation. copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 13 product folder links: ucc27211a level shift uvlo uvlo 5 3 8 4 6 7 2 1 hi li v dd hb ho hs lo v ss
ucc27211a slusbl4c ? august 2013 ? revised october 2015 www.ti.com feature description (continued) 8.3.5 output stages the output stages are the interface to the power mosfets in the power train. high slew rate, low resistance and high peak current capability of both output drivers allow for efficient switching of the power mosfets. the low- side output stage is referenced from v dd to v ss and the high side is referenced from v hb to v hs . 8.4 device functional modes the device operates in normal mode and uvlo mode. see the undervoltage lockout (uvlo) section for information on uvlo operation mode. in the normal mode the output state is dependent on states of the hi and li pins. table 2 lists the output states for different input pin combinations. table 2. device logic table hi pin li pin ho (1) lo (2) l l l l l h l h h l h l h h h h (1) ho is measured with respect to hs. (2) lo is measured with respect to vss. 14 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: ucc27211a
ucc27211a www.ti.com slusbl4c ? august 2013 ? revised october 2015 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information to affect fast switching of power devices and reduce associated switching power losses, a powerful gate driver is employed between the pwm output of controllers and the gates of the power semiconductor devices. also, gate drivers are indispensable when it is impossible for the pwm controller to directly drive the gates of the switching devices. with the advent of digital power, this situation will be often encountered because the pwm signal from the digital controller is often a 3.3-v logic signal which cannot effectively turn on a power switch. level shifting circuitry is needed to boost the 3.3-v signal to the gate-drive voltage (such as 12 v) in order to fully turn on the power device and minimize conduction losses. traditional buffer drive circuits based on npn/pnp bipolar transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate with digital power because they lack level-shifting capability. gate drivers effectively combine both the level-shifting and buffer-drive functions. gate drivers also find other needs such as minimizing the effect of high-frequency switching noise by locating the high-current driver physically close to the power switch, driving gate-drive transformers, and controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving gate charge power losses from the controller into the driver. finally, emerging wide band-gap power device technologies such as gan based switches, which are capable of supporting very high switching frequency operation, are driving very special requirements in terms of gate drive capability. these requirements include operation at low vdd voltages (5 v or lower), low propagation delays and availability in compact, low-inductance packages with good thermal capability. gate-driver devices are extremely important components in switching power, and they combine the benefits of high-performance, low-cost component count and board-space reduction as well as simplified system design. 9.2 typical application figure 18. ucc27211a typical application diagram copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 15 product folder links: ucc27211a pwm controller +12v isolation and feedback +100v secondary side circuit hi control drive lo drive hi v dd ucc27211a vss li hbho hs lo udg-13114
ucc27211a slusbl4c ? august 2013 ? revised october 2015 www.ti.com typical application (continued) figure 19. ucc27211 typical application diagram 9.2.1 design requirements table 3. design specifications design parameter example value supply voltage, vdd 12 v voltage on hs, vhs 0 v to 100 v voltage on hb, vhb 12 v to 112 v output current rating, io ? 4 a to 4 a operating frequency 500 khz 16 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: ucc27211a pwm controller +12v +100v secondary side circuit hi control drive lo drive hi v dd ucc27211 vss li hb ho hs lo +12v hi control drive lo drive hi vdd ucc27211 li hb ho hs lo +100v
ucc27211a www.ti.com slusbl4c ? august 2013 ? revised october 2015 9.2.2 detailed design procedure 9.2.2.1 input threshold type the ucc27211a has an input maximum voltage range from ? 10 v to 20 v. this increased robustness means that both parts can be directly interfaced to gate drive transformers. the ucc27211a features ttl compatible input threshold logic with wide hysteresis. the threshold voltage levels are low voltage and independent of the vdd supply voltage, which allows compatibility with both logic-level input signals from microcontrollers as well as higher-voltage input signals from analog controllers. see the electrical characteristics table for the actual input threshold voltage levels and hysteresis specifications for the ucc27211a device. 9.2.2.2 v dd bias supply voltage the bias supply voltage to be applied to the vdd pin of the device should never exceed the values listed in the absolute maximum ratings table. however, different power switches demand different voltage levels to be applied at the gate terminals for effective turnon and turnoff. with certain power switches, a positive gate voltage may be required for turnon and a negative gate voltage may be required for turnoff, in which case the vdd bias supply equals the voltage differential. with a wide operating range from 8 v to 17 v, the ucc27211a device can be used to drive a variety of power switches, such as si mosfets, igbts, and wide-bandgap power semiconductors (such as gan, certain types of which allow no higher than 6 v to be applied to the gate terminals). 9.2.2.3 peak source and sink currents generally, the switching speed of the power switch during turnon and turnoff should be as fast as possible in order to minimize switching power losses. the gate driver device must be able to provide the required peak current for achieving the targeted switching speeds with the targeted power mosfet. the system requirement for the switching speed is typically described in terms of the slew rate of the drain-to-source voltage of the power mosfet (such as dv ds /dt). for example, the system requirement might state that a spp20n60c3 power mosfet must be turned-on with a dv ds /dt of 20v/ns or higher with a dc bus voltage of 400 v in a continuous- conduction-mode (ccm) boost pfc-converter application. this type of application is an inductive hard-switching application and reducing switching power losses is critical. this requirement means that the entire drain-to- source voltage swing during power mosfet turnon event (from 400 v in the off state to v ds(on) in on state) must be completed in approximately 20 ns or less. when the drain-to-source voltage swing occurs, the miller charge of the power mosfet (qgd parameter in spp20n60c3 data sheet is 33 nc typical) is supplied by the peak current of gate driver. according to power mosfet inductive switching mechanism, the gate-to-source voltage of the power mosfet at this time is the miller plateau voltage, which is typically a few volts higher than the threshold voltage of the power mosfet, v gs(th) . to achieve the targeted dv ds /dt, the gate driver must be capable of providing the q gd charge in 20 ns or less. in other words a peak current of 1.65 a (= 33 nc / 20 ns) or higher must be provided by the gate driver. the ucc27211a gate driver is capable of providing 4-a peak sourcing current which clearly exceeds the design requirement and has the capability to meet the switching speed needed. the 2.4 overdrive capability provides an extra margin against part-to-part variations in the q gd parameter of the power mosfet along with additional flexibility to insert external gate resistors and fine tune the switching speed for efficiency versus emi optimizations. however, in practical designs the parasitic trace inductance in the gate drive circuit of the pcb will have a definitive role to play on the power mosfet switching speed. the effect of this trace inductance is to limit the di/dt of the output current pulse of the gate driver. in order to illustrate this, consider output current pulse waveform from the gate driver to be approximated to a triangular profile, where the area under the triangle ( ? i peak time) would equal the total gate charge of the power mosfet (qg parameter in spp20n60c3 power mosfet datasheet = 87 nc typical). if the parasitic trace inductance limits the di/dt then a situation may occur in which the full peak current capability of the gate driver is not fully achieved in the time required to deliver the qg required for the power mosfet switching. in other words the time parameter in the equation would dominate and the i peak value of the current pulse would be much less than the true peak current capability of the device, while the required qg is still delivered. because of this, the desired switching speed may not be realized, even when theoretical calculations indicate the gate driver is capable of achieving the targeted switching speed. thus, placing the gate driver device very close to the power mosfet and designing a tight gate drive-loop with minimal pcb trace inductance is important to realize the full peak-current capability of the gate driver. copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 17 product folder links: ucc27211a
ucc27211a slusbl4c ? august 2013 ? revised october 2015 www.ti.com 9.2.2.4 propagation delay the acceptable propagation delay from the gate driver is dependent on the switching frequency at which it is used and the acceptable level of pulse distortion to the system. the ucc27211a features 16-ns (typical) propagation delays, which ensures very little pulse distortion and allows operation at very high-frequencies. see the electrical characteristics table for the propagation and switching characteristics of the ucc27211a device. 9.2.2.5 power dissipation power dissipation of the gate driver has two portions as shown in equation 1 . p diss = p dc + p sw (1) the dc portion of the power dissipation is pdc = i q vdd where i q is the quiescent current for the driver. the quiescent current is the current consumed by the device to bias all internal circuits such as input stage, reference voltage, logic circuits, protections, and also any current associated with switching of internal devices when the driver output changes state (such as charging and discharging of parasitic capacitances, parasitic shoot-through, and so forth). the ucc27211a features very low quiescent currents (less than 0.17 ma, refer to the electrical characteristics table and contain internal logic to eliminate any shoot-through in the output driver stage. thus the effect of the pdc on the total power dissipation within the gate driver can be safely assumed to be negligible. the power dissipated in the gate-driver package during switching (psw) depends on the following factors: ? gate charge required of the power device (usually a function of the drive voltage vg, which is very close to input bias supply voltage vdd) ? switching frequency ? use of external gate resistors. when a driver device is tested with a discrete, capacitive load calculating the power that is required from the bias supply is fairly simple. the energy that must be transferred from the bias supply to charge the capacitor is given by equation 2 . eg = ? c load v dd 2 where ? c load is load capacitor ? v dd is bias voltage feeding the driver (2) there is an equal amount of energy dissipated when the capacitor is charged and when it is discharged. this leads to a total power loss given by equation 3 . pg = c load v dd 2 f sw where ? f sw is the switching frequency (3) the switching load presented by a power mosfet/igbt is converted to an equivalent capacitance by examining the gate charge required to switch the device. this gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain voltage of the power device as it switches between the on and off states. most manufacturers provide specifications of typical and maximum gate charge, in nc, to switch the device under specified conditions. using the gate charge qg, determine the power that must be dissipated when switching a capacitor which is calculated using the equation q g = c load v dd to provide equation 4 for power. p g = c load v dd 2 f sw = q g v dd f sw (4) this power p g is dissipated in the resistive elements of the circuit when the mosfet/igbt is being turned on and off. half of the total power is dissipated when the load capacitor is charged during turnon, and the other half is dissipated when the load capacitor is discharged during turnoff. when no external gate resistor is employed between the driver and mosfet/igbt, this power is completely dissipated inside the driver package. with the use of external gate-drive resistors, the power dissipation is shared between the internal resistance of driver and external gate resistor. 18 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: ucc27211a
ucc27211a www.ti.com slusbl4c ? august 2013 ? revised october 2015 9.2.3 application curves figure 20. negative 10-v input figure 21. step input figure 22. symmetrical uvlo copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 19 product folder links: ucc27211a
ucc27211a slusbl4c ? august 2013 ? revised october 2015 www.ti.com 10 power supply recommendations the bias supply voltage range for which the ucc27211a device is recommended to operate is from 8 v to 17 v. the lower end of this range is governed by the internal undervoltage-lockout (uvlo) protection feature on the v dd pin supply circuit blocks. whenever the driver is in uvlo condition when the v dd pin voltage is below the v (on) supply start threshold, this feature holds the output low, regardless of the status of the inputs. the upper end of this range is driven by the 20-v absolute maximum voltage rating of the v dd pin of the device (which is a stress rating). keeping a 3-v margin to allow for transient voltage spikes, the maximum recommended voltage for the v dd pin is 17 v. the uvlo protection feature also involves a hysteresis function, which means that when the v dd pin bias voltage has exceeded the threshold voltage and device begins to operate, and if the voltage drops, then the device continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification v dd(hys) . therefore, ensuring that, while operating at or near the 8-v range, the voltage ripple on the auxiliary power supply output is smaller than the hysteresis specification of the device is important to avoid triggering device shutdown. during system shutdown, the device operation continues until the v dd pin voltage has dropped below the v (off) threshold, which must be accounted for while evaluating system shutdown timing design requirements. likewise, at system start-up the device does not begin operation until the v dd pin voltage has exceeded the v (on) threshold. the quiescent current consumed by the internal circuit blocks of the device is supplied through the v dd pin. although this fact is well known, it is importatnt to recognize that the charge for source current pulses delivered by the ho pin is also supplied through the same v dd pin. as a result, every time a current is sourced out of the ho pin, a corresponding current pulse is delivered into the device through the v dd pin. thus, ensure that a local bypass capacitor is provided between the v dd and gnd pins and located as close to the device as possible for the purpose of decoupling is important. a lo-esr, ceramic surface-mount capacitor is required. ti recommends using a capacitor in the range 0.22 f to 4.7 f between v dd and gnd. in a similar manner, the current pulses delivered by the lo pin are sourced from the hb pin. therefore a 0.022- f to 0.1- f local decoupling capacitor is recommended between the hb and hs pins. 11 layout 11.1 layout guidelines to improve the switching characteristics and efficiency of a design, the following layout rules must be followed. ? locate the driver as close as possible to the mosfets. ? locate the v dd ? v ss and v hb -v hs (bootstrap) capacitors as close as possible to the device (see figure 23 ). ? pay close attention to the gnd trace. use the thermal pad of the drm package as gnd by connecting it to the vss pin (gnd). the gnd trace from the driver goes directly to the source of the mosfet, but must not be in the high current path of the mosfet drain or source current. ? use similar rules for the hs node as for gnd for the high-side driver. ? for systems using multiple and ucc27211a devices, ti recommends that dedicated decoupling capacitors be located at v dd -v ss for each device. ? care must be taken to avoid placing vdd traces close to lo, hs, and ho signals. ? use wide traces for lo and ho closely following the associated gnd or hs traces. a width of 60 to 100 mils is preferable where possible. ? use as least two or more vias if the driver outputs or sw node must be routed from one layer to another. for gnd, the number of vias must be a consideration of the thermal pad requirements as well as parasitic inductance. ? avoid li and hi (driver input) going close to the hs node or any other high dv/dt traces that can induce significant noise into the relatively high impedance leads. a poor layout can cause a significant drop in efficiency or system malfunction, and it can even lead to decreased reliability of the whole system. 20 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: ucc27211a
ucc27211a www.ti.com slusbl4c ? august 2013 ? revised october 2015 11.2 layout example figure 23. ucc27211a pcb layout example 11.3 thermal considerations the useful range of a driver is greatly affected by the drive-power requirements of the load and the thermal characteristics of the package. for a gate driver to be useful over a particular temperature range, the package must allow for efficient removal of the heat produced while keeping the junction temperature within rated limits. the thermal metrics for the driver package are listed in thermal information . for detailed information regarding the table, refer to the application note from texas instruments entitled semiconductor and ic package thermal metrics ( spra953 ). the ucc27211a device is offered in soic (8) and vson (8). the thermal information section lists the thermal performance metrics related to the sot-23 package. copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 21 product folder links: ucc27211a ucc2721x
ucc27211a slusbl4c ? august 2013 ? revised october 2015 www.ti.com 12 device and documentation support 12.1 documentation support 12.1.1 related documentation the reference and link to additional information may be found at www.ti.com . ? additional layout guidelines for pcb land patterns may be found in, qfn/son pcb attachment , application brief ( slua271 ) 12.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.3 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 12.4 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. 22 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: ucc27211a
package option addendum www.ti.com 21-sep-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples ucc27211ad preview soic d 8 75 tbd call ti call ti -40 to 140 27211a ucc27211adr preview soic d 8 2500 tbd call ti call ti -40 to 140 27211a ucc27211adrmr active vson drm 8 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 140 27211a ucc27211adrmt active vson drm 8 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 140 27211a (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and
package option addendum www.ti.com 21-sep-2015 addendum-page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ucc27211adrmr vson drm 8 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 q2 ucc27211adrmt vson drm 8 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 q2 package materials information www.ti.com 29-jun-2015 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ucc27211adrmr vson drm 8 3000 367.0 367.0 35.0 ucc27211adrmt vson drm 8 250 210.0 185.0 35.0 package materials information www.ti.com 29-jun-2015 pack materials-page 2

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